1. Technical Field of the Invention
The present invention relates to a reference current generator. More particularly, the invention relates to a first order temperature compensated, and process corner and power supply independent, reference current generator for low voltage applications in CMOS technology.
2. Description of Related Art
A current reference is normally obtained from a bandgap reference circuit as shown in FIG. 1. A bandgap circuit generally has diode-connected Bipolar Junction Transistors (BJTs) Q0, Q1, Q3 and Q4 connected in parallel to each other. BJT Q0 is provided with a series connected resistor R1, whereas BJT Q4 is provided with a resistor connected in parallel to achieve a current summing function. A current device comprising transistors M1, M2, M12 and M13 causes a similar current to flow through each of these BJTs. An operational amplifier OP1 receives input from BJTs Q0 and Q1 as shown. The output Y0 of the operational amplifier OP1 is connected to the control terminals of current devices M1, M2 and M13 for regulating the current supplied by the device. Another operational amplifier OP2 is connected to the emitters of BJTs Q2 and Q3. The output Y1 of this operational amplifier is connected to the control terminal of transistor M12. The function of this arrangement is to maintain the input nodes of operational amplifiers OP1 and OP2 at same voltage level. The output current I can be than be mirrored from this circuit.
The current equation for this circuit can be written asI=(Vt*ln(n)/R1)+Vbe/R2where, Vt is the thermal voltage (26 mV at 300 deg K); Vbe is the base emitter voltage drop of a BJT; and n is the emitter area ratio of BJTS Q0 and Q1.
The current I is temperature compensated to the first order as both Vt and Vbe have inverse temperature dependencies, however an approximately +/−20% variation of this current is observed across process, voltage and temperature (PVT).
The minimum supply voltage required for a typical 90 nm process, is the voltage drop across base emitter voltage drop of the BJT Vbe (typically 0.65V) plus the threshold voltage of the Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Vth (approximately 0.25V) plus twice the drop across drain to source voltage for a MOSFET to operate in saturation Vds(sat). Mathematically this minimum supply voltage Vdd required can be written as:Vdd(min)=Vbe+Vth+2*Vds(sat)
From the above discussion it is apparent that a substantial voltage drop is observed across the BJTs. For low voltage applications having supply voltage of about 1 Volt this poses a serious limitation as the voltage headroom available for the MOS to operate in saturation is almost unavailable or is so small that the required sizes of the MOS transistors become very large. This increases the parasitics associated with the MOS transistors. Further as each MOS transistor is expected to operate at the edge of saturation the output resistance of the MOS transistor is very small and the overall performance of the circuit is affected. Therefore reliability of this circuit for low voltage applications is very low.
U.S. Pat. No. 6,448,844, the disclosure of which is hereby incorporated by reference, describes another CMOS current reference 100 shown in FIG. 2. This circuit includes a constant current generating unit 110 for generating a current that is proportional to absolute temperature (PTAT) that does not depend on the supply voltage VDD. Further the invention includes a self-compensation unit MP9 for controlling the constant current generating unit 110 to maintain the constant current regardless of the variation in temperature. The CMOS current reference circuit also includes a starting circuit unit MN5 for establishing a current path to activate the constant current generating unit 110 and a constant current outputting unit 120 for supplying the bias current Ibias generated from the constant current generating unit 110. A variable resistor 112 is coupled between the drain of the NMOS transistor MN7 and ground VSS. In order to prevent the output bias current Ibias from varying due to process variations, a variable resistor 112 comprising of a plurality of parallel resistors R1, R2 . . . , Rn is provided to adjust the resistance value depending on the process variation as shown in FIG. 2a. 
An expression for the current I generated by circuit in FIG. 2 can be derived by assuming transistor MN5 carries negligible current. Transistors MP6 and MP7 form a current mirror. It is assumed that the equivalent resistance of the variable resistor is R and the currents in transistors MN6B and MP9 are I1 and I2 respectively. The resistor 112 is coupled between the drain of the NMOS transistor MN7 and VSS. For the purpose of derivation of the relationship the following parameter definitions are used:                Vt=thermal voltage (26 mv at 300 deg K);        Vbe=base emitter voltage drop of the BJT;        Vgs=gate to source voltage of a MOS;        Vds=drain to source voltage of a MOS;        κn=transconductance parameter of a NMOS;        κp=transconductance parameter of a PMOS;        μn=surface mobility of electrons in a NMOS;        κp=surface mobility of electrons in a PMOS;        Vth=threshold voltage of a MOS;        Cox=gate oxide capacitance per unit area of a MOS;        gm=small signal transconductance of a MOS;        rds=small signal output resistance of a MOS;        W/L=Width Vs Length ratio of a transistor;wherein:VgsMN6B=VsgMP9=VgsMN7+I*RVgsMN6B=√2*I1/βMN6B+Vthnwhere βMN6B=κn(T)*(W/L)MN6Bκn(T)=μn(T)*Coxμn(T)=μn0* T(−3/2)VsgMP9=√2*I2/βMP9+Vthpwhere βMP9=κp(T)*(W/L)MN6Bκp(T)=μp(T)*CoxVgsMN7=√2*I/βMN7+Vthn        
Assuming that the threshold voltages for the n and p type MOS transistors are the same, that is:Vthn=VthpThe following expression is obtained:I=(2/R2*(βMN6B+βMP9))*(1−√(βMN6B+βMP9)/(βMN7))2
From the above equation it is evident that the current I is first order compensated only if the resistance used has a positive temperature coefficient. For a particular process both positive temperature coefficient and negative temperature coefficient resistances would be available and to get a first order compensated current using 100 a positive temperature coefficient resistance has to be chosen. Normally in a particular process negative temperature coefficient resistances exhibit less variation across the process corners than the positive temperature coefficient resistances. A positive temperature coefficient resistance results in a large variation of current across process corners.
The circuit also exhibits poor supply rejection and hence current variation with supply voltage. The start up transistor MN5 is not switched off during steady state operation leading to a offset in the values of the currents in the two branches of the constant current generating unit 110 and to increased dependence of the current on the supply voltage. Also there is a potential short circuit path from VDD to VSS formed by MN5 and MP9 leading to large power dissipation.
There is accordingly a need to obviate the above and other drawbacks in the prior art.